The present invention relates to a variable delay circuit for use in, for example, a timing generator of an IC tester and, more particularly, to a variable delay circuit which is adapted to provide a fine delay corresponding to set data.
FIG. 1 shows a timing generating circuit which forms a part of a timing generator for use in conventional IC testers. One of IC tests is to examine the range of timing over which an IC under test is able to operate correctly, by changing the timing of an input signal to the IC. In such a test, a rate signal S.sub.R of a fixed period (a test cycle period), which has reference timing, is delayed for desired periods of time one after another, by which a timing signal S.sub.T for determining the timing of the input signal to the IC is provided from such a timing generating circuit as shown in FIG. 1. That is, the rate signal S.sub.R of a fixed period, for example, in the range of 10 to 100 ns, which represents reference timing of the test cycle, is provided to a terminal 11S, and in synchronization with this, delay setting data D is provided to a terminal 11D. Data D.sub.H of high order m bits of the delay data D represents a coarse delay in units of the period of a clock CLK shorter than the test cycle, for example, 4 ns or so, and the data D.sub.H is set in a latch circuit 14. Data D.sub.L of low order n bits of the delay data D represents a fine delay which is shorter than the period of the clock CLK, and the data D.sub.L is provided to a fine variable delay circuit 16 to which the present invention pertains.
Upon each application of the rate signal S.sub.R from the terminal 11S, a counter 12 is reset and counts the clock CLK from a terminal 13. When the count value of the counter 12 coincides with the data D.sub.H set in the latch circuit 14, the coincidence is detected by a coincidence detector 15, which outputs a coincidence detection pulse S.sub.P. Consequently, the coincidence detection pulse S.sub.P lags behind the rate signal S.sub.R by about D.sub.H (a binary number) times the period of the clock CLK. The coincidence detection pulse S.sub.P is applied to the fine variable delay circuit 16, wherein it is delayed for a time shorter than one period of the clock CLK in accordance with the low n-bit data D.sub.L of the delay setting data D, and the delayed output is provided as a timing signal S.sub.T. In this way, the timing signal S.sub.T is generated which is delayed behind the rate signal S.sub.R at the terminal 11S by the period of time corresponding to the set data D.
The fine variable delay circuit 16 comprises a cascade connection of n delay stages 21 in each of which a path selector 19 selects either one of a path which passes through a delay element 17 and a path 18 which does not pass therethrough. The respective path selectors 19 are controlled by corresponding bits of n-bit control data D.sub.c which is provided from a conversion table 22. Usually, the delay elements 17 are each formed by a gate array (AND gates, OR gates, or inverters, or a combination thereof) which provides a desired propagation delay t.sub.p d, that is, the delay stages 21 provide delays having weight 2.sup.0, 2.sup.1, . . . , 2.sup.n-1 in ascending order. Delays corresponding to all possible paths in the cascade connection of the delay stages 21, that is, delays corresponding to all possible values of the n-bit control data D.sub.c are measured and the relationship between the set data D.sub.L of the desired delay and the control data D.sub.c for controlling the path selector 19 to obtain a measured composite delay closest to the desired delay is obtained in advance, and this relationship is prestored as a conversion table in the conversion table memory 22. In practice, there are written the control data D.sub.c at the corresponding addresses D.sub.L in the conversion able memory 22, using the set data D.sub.L as addresses. In the following description the term "conversion table" may be used to indicate the conversion table memory in some cases. The set data D.sub.L is used as an address to read out the corresponding control data D.sub.c from the conversion table memory 22, and the path selectors 19 are controlled by the corresponding bits of the control data D.sub.c to obtain a composite delay closest to the desired delay corresponding to the set data.
The delay of the delay element 17 varies with a temperature change. On this account, if ambient temperature substantially varies from ambient temperature at which the conversion table 22 was produced, then a large error will be induced in the composite delay which is provided corresponding to the low-order bit data D.sub.L (hereinafter referred to simply as set data). For example, when ambient temperature rises, the delay increases at a fixed rate, whereas when the temperature lowers, the delay decreases at the fixed rate. For instance, assuming that the delay intended to obtain with respect to the set data D.sub.L =1001 is 900 ps, the control data D.sub.c obtainable from the conversion table 22 is 0111 and the actual composite delay obtainable in this case is 875 ps, then the error is 25 ps, but if the composite delay obtainable with the control data 0111 becomes 950 ps due to an increase in ambient temperature, then the error will increase to 50 ps with respect to the intended delay 900 ps.
When such a large error is induced in the composite delay, that is, when ambient temperature varies in excess of a predetermined value, it is conventional to measure the composite delay corresponding to all control data D.sub.c and rewrite the conversion table memory 22 from a control part 10. However, in the case where the number of delay stages 21 is, for example, 10, that is, where the set data D.sub.L is 10-bit, the composite delay must be measured as many as 2.sup.10 times, and consequently, much time is needed to rewrite the conversion table memory 22; therefore, it is difficult, in practice, to rewrite the conversion table memory 22 frequently. Conventionally, the conversion table memory 22 is rewritten, for example, when ambient temperature varies 5.degree. C., but an appreciable large error is induced even by a temperature change within 5.degree. C. Moreover, when ambient temperature undergoes a substantial change relatively quickly, the conversion table memory 22 must be rewritten frequently, and consequently, the variable delay circuit cannot efficiently be used. This problem is particularly serious in the case of employing a number of fine variable delay circuits 16 for setting specified delays with respect to the high-speed rate signal S.sub.R as in the case of a timing generator of an IC tester which requires many timing signals.